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    JESD47L中英文 Stress-Test-Driven Qualification of Integrated Circuits

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  • JESD47L.pdf    2022 12月

    JESD47L

    (Revision of JESD47K dated August 2018)

    JESD47L中英文 Stress-Test-Driven Qualification of Integrated Circuits

    JESD47L中英文.pdf

    JESD47L中英文 Stress-Test-Driven Qualification of Integrated Circuits

    This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

    这个文档描述了用于考核新产品、同族器件或工艺变更的可接受的基准测试标准

    These tests are capable of stimulating and precipitating semiconductor device and packaging failures. The objective is to precipitate failures in an accelerated manner compared to use conditions. Failure Rate projections usually require larger sample sizes than are called out in qualification testing. For guidance on projecting failure rates, refer to JESD85 Methods for Calculating Failure Rates in Units of FITs. This qualification standard is aimed at a generic qualification for a range of use conditions, but is not applicable at extreme use conditions such as military applications, automotive under-the-hood applications, or uncontrolled avionics environments, nor does it address 2 nd level reliability considerations,

    which are addressed in JEP150. Where specific use conditions are established, qualification testing tailored to meet those specific requirements can be developed, using JESD94 that will result in a better optimization of resources.

    这些测试用于加速和诱发半导体器件和封装的失效。目的是通过比使用环境相比加速的方式来促

    成失效。相比考核测试,失效率的预测需要更多的样品数量。如果需要计算预期的失效率,请参

    考JESD85 Methods for Calculating Failure Rates in Units of FITs 。本考核标准用于制定一系列适用于 一般使用环境下的通用考核标准,而不是用于例如军工应用,汽车电子,或者不受控的航天电子

    等极端使用环境;同时本标准也不解决JEP150标准中提出的2nd 等级可靠性问题。在确定具体使

    用条件的情况下,可以使用JESD94开发适合于满足这些特定要求的考核测试,从而更好地优化测

    试资源。

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